High-speed parallel data transmission through interconnect devices and backplanes often suffers from co-channel interference and EMI effects. In particular, skew becomes problematic because the phase relationship between data and clock can be lost as a result of differing travel times within the parallel data channel. As a result, such high-speed parallel data may be serialized before transmission and de-serialized upon reception using serial transmission protocols such as low voltage differential signaling (LVDS) or low voltage current mode signaling (CML).
In an LVDS or CML system, the clock may be embedded within the encoded data, thereby eliminating the skew problem associated with parallel data transmission. To permit the transition between parallel and serial data transmission, serializer/deserializer (SERDES) units are incorporated at both the transmitting and receiving ends of the serial data stream. Despite the advantages provided by serializing the data, certain disadvantages remain. For example, assume that the parallel data is 32 bits wide (thereby forming a 32 bit word) and the word rate is 125 MHz. A SERDES receiving such a parallel data stream would have to provide a serial data stream encoding a 4 GHz bit stream. A conventional SERDES serial channel can run no better than 2 GHz, however. Thus, two SERDES serial channels would be needed—e.g., the most significant 16 bits in each 32 bit word from the parallel data stream could be sent on a first serial channel and the least significant 16 bits could be sent on a second serial channel.
Although a SERDES accommodating such multiple serial channels may be constructed, it introduces a similar problem inherent in the parallel data stream because each serial channel may be incoherent to its companion serial channels. Thus, the multiple serial channels are synchronized by an initial locking signal, which aligns the multiple bitstreams at the receiving SERDES units. This alignment within SERDES applications is typically denoted as “channel lock.”
In applications employing multiple serial channels, synchronization schemes to maintain channel lock typically have employed one of two approaches. In a first approach, the data is “packetized” before transmission. Before sending a packet, the transmitter sends a locking signal and establishes a one-way synchronized connection. The packet is then sent. In an analogous fashion, the receiver sends a response packet on its corresponding transmit link. Depending upon the application, the response packet may acknowledge receipt (ack), indicate failure (nack), or otherwise indicate the state of the receive side link. Such a sequence of events is fundamental to packet-switched networks. Although robust with respect to each packet, this first approach suffers from redundancy—for each packet, the locking signal is transmitted regardless of whether the link was already locked. Such redundancy slows the overall data transmission rate.
In a second approach, the high-speed serial channels are regarded as unreliable so that a second channel, which is more stable (and presumably more reliable) than the serial channels is used to communicate feedback from one SERDES to another. In this fashion, a transceiver communicating to another transceiver through a SERDES-coupled serial channel may be assured that it transmits a properly synchronized signal or told to resynchronize the channel. Although this second approach does not suffer the redundancy of the first approach, it requires the hardware and support necessary for the extra (out-of-band) channel.
Accordingly, there is a need in the art for improved methods to initiate and maintain channel lock in serial applications.